From the appearance of integrated transistor in the electronic industry, digital systems performance has spectacularly advanced year after year. Progressive miniaturization of CMOS processes maintains this growth because smaller transistor sizes allow higher operating frequencies and the integration of more complex logic functions in the same silicon die. Unfortunately, nowadays this paradigm is changing. Transistors are now as tiny that their characteristics in terms of power consumption and delay are comparable to those associated to the connections between them. This situation forces designers to take special care when implementing metal interconnections. The problem is particularly critical when we consider the huge skew-free clock distribution networks that are implemented in complex chip designs. These networks not only consume an enormous amount of power, but also cause a harmful electromagnetic interference (EMI) that can affect their own correct operation and those of others systems surrounding them. In order to cope with this situation, engineers are focusing their attention towards the implementation of Globally Asynchronous Locally Synchronous systems. In these specially designed systems, clock network is split into different synchronous clock domains with asynchronous circuitry controlling their correct coordination.
In the last years, as Field Programmable Gate Arrays are being implemented in deep submicron processes, we can extrapolate that issue to this special class of electronic devices. Contrarily to full-custom design, engineers trying to deploy GALS systems into commercially available FPGAs must deal with a fixed architecture that determines the different kinds of asynchronous circuitry that can be implemented in an efficient way. This situation drives irremediably to a logic resources overhead that precludes the use of GALS approach over these devices for commercial applications.
In the AsyncArt project, we will try to overcome these issues by introducing a new GALS approach for programmable devices that is strongly inspired by the CMOS GasP minimal control protocol for FIFO micropipelines. In this way, we have designed a General Purpose Rendezvous Module (GPRM) aimed to match with the fixed architecture of commercial LUT-based FPGAs. This module has added functionalities over the standard straight-forward FIFO control like clock pulse generation for self-timed operation of independent synchronous blocks and smart real-time cycle length selection for implementing EMI spread spectrum and throughput control techniques.